1. Field of the Invention
The present invention relates to the field of semiconductor memory devices and, more particularly to a multiplexed noisy-quiet power busing scheme for improved area efficiency and pause performance in dynamic random access memories.
2. Description of the Related Art
An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 10. Each cell 10 contains a storage capacitor 14 and an access field effect transistor or transfer device 12. For each cell, one side of the storage capacitor 14 is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor 14 is connected to the drain of the transfer device 12. The gate of the transfer device 12 is connected to a signal known in the art as a word line 18. The source of the transfer device 12 is connected to a signal known in the art as a bit line 16 (also known in the art as a digit line). With the memory cell 10 components connected in this manner, it is apparent that the word line 18 controls access to the storage capacitor 14 by allowing or preventing the signal (representing a logic "0" or a logic "1") carried on the bit line 16 to be written to or read from the storage capacitor 14. Thus, each cell 10 contains one bit of data (i.e., a logic "0" or logic "1").
Referring to FIG. 2, an exemplary DRAM circuit 40 is illustrated. The DRAM 40 contains a memory array 42, row and column decoders 44, 48 and a sense amplifier circuit 46. The memory array 42 consists of a plurality of memory cells (constructed as illustrated in FIG. 1) whose word lines and bit lines are commonly arranged into rows and columns, respectively. The bit lines of the memory array 42 are connected to the sense amplifier circuit 46, while its word lines are connected to the row decoder 44. Address and control signals are input into the DRAM 40 and connected to the column decoder 48, sense amplifier circuit 46 and row decoder 44 and are used to gain read and write access, among other things, to the memory array 42.
The column decoder 48 is connected to the sense amplifier circuit 46 via control and column select signals. The sense amplifier circuit 46 receives input data destined for the memory array 42 and outputs data read from the memory array 42 over input/output (I/O) data lines. Data is read from the cells of the memory array 42 by activating a word line (via the row decoder 44), which couples all of the memory cells corresponding to that word line to respective bit lines, which define the columns of the array. One or more bit lines are also activated. When a particular word line is activated, the sense amplifier circuit 46 connected to a bit line column detects and amplifies the data bit transferred from the storage capacitor of the memory cell to its bit line by measuring the potential difference between the activated bit line and a reference line which may be an inactive bit line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
Typically, the memory of a DRAM is subdivided into quadrants of memory. A quadrant may contain a bank, partial bank, multiple banks or multiple partial banks. In addition, a bank will contain one or more sub arrays. FIG. 3 illustrates the DRAM 40 with a memory array 42.DELTA. that is subdivided into four quadrants Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4. FIG. 4 illustrates how the DRAM memory quadrants are also often further subdivided into sub arrays S.sub.1, S.sub.2, . . . S.sub.N. Each sub array S.sub.1, S.sub.2, . . . S.sub.N is connected to respective local row decoders 44.sub.1, 44.sub.2, . . . 44.sub.N and sense amplifier circuits 46.sub.1, 46.sub.2, . . . 46.sub.N (other circuitry such as a column decoder and the I/O lines are not shown). In addition, a gap 58.sub.1, 58.sub.2, . . . 58.sub.N is found at respective intersections of the local row decoders 44.sub.1, 44.sub.2, . . . 44.sub.N and sense amplifier circuits 46.sub.1, 46.sub.2, . . . 46.sub.N for each sub array S.sub.1, S.sub.2, . . . S.sub.N. Although not required, these gaps 58.sub.1, 58.sub.2, . . . 58.sub.N typically include sense amplifier control circuitry (illustrated in FIG. 5) used to control associated sense amplifier circuits 46.sub.1, 46.sub.2, . . . 46.sub.N. The sense amplifier control circuitry is usually contained within the gaps 58.sub.1, 58.sub.2, . . . 58.sub.N to conserve precious space on the DRAM chip.
Referring now to FIGS. 4 and 5, a control circuit 60 is connected to the sense amplifier control circuitry 64 of each gap 58.sub.1, 58.sub.2, . . . 58.sub.N (designated in FIG. 5 as gap 58.sub.X) via sense amplifier control lines LPSA_, LNSA. The sense amplifier control circuit 64 (FIG. 5) contains a p-channel metal-oxide semiconductor field-effect transistor (MOSFET) 66 and an n-channel MOSFET 68. A voltage bus, designated generally as V.sub.CC or V.sub.CC bus, is connected to a source terminal of the p-channel MOSFET 66. A ground potential bus, designated generally as GND or GND bus, is connected to a source terminal of the n-channel MOSFET 68. It should be noted that the sense amplifier control circuitry 64 would also contain additional circuitry, such as conventional biasing circuitry, but the additional circuitry is not pertinent to the present invention.
The first sense amplifier control signal LPSA_ is used to activate the p-channel MOSFET 66 during a row activation process. When activated, the MOSFET 66 switches in the voltage from the V.sub.CC bus to generate a p-sense amplifier activation signal ACT. As is known in the art, the p-sense amplifier activation signal ACT is used to activate a p-sense amplifier portion (not shown) of the sense amplifier circuit 46.sub.X during a row activation operation. The second sense amplifier control signal LNSA is used to activate the n-channel MOSFET 68 during a row activation operation. When activated, the MOSFET 68 switches in the ground potential from the GND bus to generate an n-sense amplifier activation signal RNL_. As is known in the art, the n-sense amplifier activation signal RNL_ is used to activate an n-sense amplifier portion (not shown) of the sense amplifier circuit 46.sub.X during a row activation operation. It should be appreciated that the particular circuitry of the sense amplifier circuit 46.sub.X is not pertinent to the practice of the invention.
Referring to FIG. 6, it can be seen that prior to the generation of the p-sense amplifier activation signal ACT and the n-sense amplifier activation signal RNL_, that the VCC bus is at a potential equivalent to Vcc, while the GND bus is at a GND potential. Immediately after the generation of the ACT and RNL_ signals, the potential of the V.sub.CC bus drops below Vcc, while the potential of the GND bus rises above the GND potential. That is, immediately after the generation of the ACT and RNL_ signals, the V.sub.CC bus experiences a "bump" down in voltage, while the GND bus experiences a "bump" up in voltage (hereinafter, these bumps will be collectively referred to as "power bumps"). These power bumps occur because there is a large current drain when the sense amplifier circuitry becomes active.
Eventually, the power pumps decay back to the Vcc and GND potentials. As shown in FIG. 6, however, a series of ACT and RNL_ signals will cause the power bumps on V.sub.CC and GND buses to get slightly larger, preventing the V.sub.CC bus from having a Vcc potential and the GND bus from having a GND potential during that time (due to the summation of decayed bumps with the present bump). In addition, both buses will experience some noise.
DRAM devices are the most cost effective high speed memory used with computers and computer systems. They are available in very high density. They are, however, limited in the longevity of their memory. DRAM devices require constant refreshing and lose all knowledge of their state (i.e., contents) once power to the device is removed. This occurs because the DRAM cells utilize capacitors, which discharge over time.
The term "pause" is often used to represent the amount of time that a DRAM cell, or group of cells, can maintain their charge without undergoing a refresh operation. That is, how long can the DRAM control circuitry pause between refresh operations and still maintain the stored state of the DRAM memory cell. It is desirable to extend the pause period of the DRAM.
A manufacturer may want to extend the pause period and thus, improve the pause performance of the DRAM to provide customers with the capability to perform more memory operations (e.g., reads and writes) between refresh cycles. This reduces the overhead required to utilize the DRAM. Moreover, a manufacturer may want to extend the pause period to improve the operating specifications of the DRAM. For example, DRAMs typically have a low-power or standby specification requiring the DRAM to operate within a maximum current during a low-power mode. Since memory cells must be refreshed during the lower-power mode, reducing the frequency of the refresh operations will improve the DRAM's operational performance for the low-power mode. Thus, there is a desire and need to improve the pause performance of DRAM memory devices.
Maximizing or minimizing the actual voltage level that a DRAM memory cell achieves for a "1" or a "0" during a write or refresh cycle is critical to achieving good pause performance. Array power busing is a part of this process. For architectures that allow separate power busing per bank (a bank meaning the maximum memory region that just one logical row can be addressed at a time), the power busing required is not too stringent since the power buses have time to recover between successive row accesses to the same bank. However, for architectures that require multiple banks to share common array power buses such as the DRAM illustrated in FIGS. 3-4, the current required to be delivered through the array power busing can increase many fold over that of a single bank-power bus scenario.
Additionally, the large power bumps that occur when a row is activated in a bank (i.e., when the p-sense and n-sense amplifier activation signals ACT, RNL_ are generated) may coincide with a row precharge operation (i.e., a refresh operation) being performed in another bank within the same array power grid. A significant portion of these power bus bumps, such as the ones illustrated in FIG. 6, transmit directly in to the memory cells of the row being precharged (also known as a row deactivation). That is, since there is a bump in the V.sub.CC and GND buses, the voltage level being stored into the cells is less than Vcc or greater than GND. This results in reduced cell voltage levels, and correspondingly reduced pause because a full charge has not been stored in the cell. As illustrated in FIG. 6, the power bumps get larger as the row activations are relatively close to each other. This further reduces the pause period and thus, pause performance of the DRAM. Accordingly, there is a desire and need for a power busing technique that improves the pause performance of DRAM memory devices.